1. Field of the Invention
This invention relates generally to data communications and the interface between a computer system and a network, and more particularly to methods and apparatuses for efficiently transmitting an asynchronous Transfer Mode (ATM) protocol data unit (PDU) over a network.
2. Description of the Related Art
ATM configured networks allow for high-speed data, voice and video communications to be conducted between endpoint computer systems. ATM networks, which are based on the transmission of fixed-length data packets, have proven to be extremely useful because they combine the benefits of both a switched network (e.g., constant transmission delay, guaranteed capacity) and a packet switched network (e.g., flexibility and efficiency for intermittent traffic).
Current ATM standards are defined by the International Telecommunication Union (ITU) ATM Forum specifications, which are hereby incorporated by reference. As is common in contemporary communications protocols, several protocol layers are used to functionally divide the communications task within an ATM network. The ATM protocol layers are similar in scope to the Open System Interconnection (OSI) reference model that is defined by the International Standardization Organization (ISO).
In ATM networks, a variable length PDU defines the data to be shared between higher protocol layers, such as the application layer software programs operating at the endpoint computer systems. A typical PDU includes the data to be shared along with additional header and trailer information. To transmit the PDU over an ATM configured network, each PDU is further divided into fixed-length transmission units, known as cells. A typical cell is 53 bytes long and includes a 5-byte header containing its' connection identifier and a 48-byte payload. Thus, for example a 480-byte PDU would be divided into ten cells, each cell having a 48 byte payload or one tenth of the PDU.
During transmission, a cell is sent from one endpoint computer system to another through a virtual circuit (VC) within the interconnecting ATM network. A VC typically consists of a concatenation of communication links established between the two endpoints where higher layer protocols are accessed. By definition, ATM cells are transmitted in a sequence over an established VC. As such, the VC must exist throughout the transmission of a PDU. One of the advantages of an ATM configured network is that a number of VCs can be established over a single wire or fiber connecting the sending computer system to the network by time-division multiplexing the cells from different PDUs.
Typically, an ATM Network Interface Card (NIC) and accompanying software are provided within the sending (or receiving) endpoint computer systems to transmit (or receive) the cells of a PDU over a VC. In terms of the OSI reference protocol model, a typical NIC provides link layer functionality by supplying cells in a specific sequence to the physical layer of the ATM network. In contrast, the VCs within the ATM network are typically established at a higher level layer, as are the PDUs and information therein.
FIG. 1a is a block diagram illustrating a typical ATM network having a first endpoint computer labeled host 12, a network 14, and one or more additional endpoint computers labeled end stations 16. Within network 14 there are illustrated, by way of dashed connecting lines, a plurality of virtual circuits 18 that represent the communication channels established between host 12 and end stations 16 during an ATM communication. By way of example, network 14 may include one or more telecommunications and/or data networks, having switching devices, routing devices, and dedicated communication lines and/or fibers that are capable of providing a communication link between host 12 and end stations 16. Host 12 and end stations 16 may, for example, be personal computer systems, workstations, mainframes, or other like processing devices that are capable of sending and receiving ATM PDUs.
FIG. 1b is a block diagram that illustrates one possible configuration of an endpoint computer system, such as host 12 in FIG. 1a, having a processor 20, a host bus 22, a system memory 24, a PCI controller 26, a PCI bus 28, a NIC 30, and an optional SCSI interface (I/F) 32 and SCSI device 34. Processor 20 can for example be a microprocessor or central processing unit (CPU) configured to access system memory 24. System memory 24 can for example be a dynamic random access memory (DRAM) that is accessed via host bus 22, or by way of another interconnecting circuit. SCSI device 34 can for example be a secondary data storage device, such as a disc drive unit, that can be accessed by processor 20 by way of host bus 22, PCI controller 26, PCI bus 28, and SCSI interface 32. As shown, processor 20 can also access network 14 by way of PCI bus 28 and NIC 30. It is recognized that additional processors and other devices and additional buses, etc., can be connected to either the host bus or PCI bus, as is common in modern computing configurations.
In a typical endpoint computer system, when the higher level protocol and/or application layers require a PDU to be transmitted over network 14 to another endpoint computer system several process steps typically occur. First, a VC is typically established by processor 20 via NIC 30. Next, the PDU is stored in system memory 24 by processor 20. Following that, NIC 30 is directed by processor 20 to complete the desired PDU transmission.
Thus, in order to complete the transmission of the PDU, in a typical configuration, NIC 30 needs to fetch the PDU data, segment it to cells, and transmit these cells, one-by-one, over a VC in network 14. As such, one important consideration in the design and operation of a NIC and associated software is the transferring (i.e., fetching) of the PDU from the memory to the NIC.
Conventional NICs can be divided into one of three groups based upon their fetching methods. The first fetching method typically includes an internal sequencer that determines the order in which the cells are to be transmitted. The cells are then fetched one at a time from host memory, stored in an on-chip first-in-first-out (FIFO) buffer, and eventually transmitted in the same order as originally fetched. This type of fetching is used, for example, in the IDT77201 available from Integrated Device Technology of Santa Clara Calif. While this type of operation tends to reduce the amount of memory required on the NIC it also tends to place an unacceptable load that burdens the interconnecting devices and buses which are required during the sequential fetching of cells from memory.
The second fetching method attempts to reduce the burden on the interconnecting devices and buses by providing enough memory on-board the NIC to store a complete PDU. Thus, with this type of NIC the entire PDU is transferred from the host memory to the on-board memory during a one time fetching cycle. This type of fetching is used, for example in the ANA-5930 series of products available from Adaptec, Inc. of Milpitas, Calif. Although this type of NIC works well at reducing the burden by minimizing the amount of time required to fetch the PDU, the amount of on-board memory required to support a plurality of VCs (i.e., simultaneously storing a plurality of PDUs) may reduce the overall effectiveness of the NIC, and/or greatly increase the NIC's cost, power consumption and size.
The third fetching method relies on the host's processor to establish and maintain a linked list of cells to be transmitted for each VC, and to continuously or periodically interface with the NIC in completing the transfer of the PDU to the NIC at the correct times. This type of fetching is supported, for example, by the MB86684 Integrated Terminal Controller available from Fujitsu, Inc. of San Jose, Calif. Unfortunately, this type of continuous or periodic operation tends to increase the burden on both the host's processor and the interconnecting devices and buses which may be further tied-up during the transferring and processing/updating operations.
Thus, what is desired are improved methods and apparatuses that effectively reduce the "fetching burden" on the interconnecting devices and buses, and/or the host's processor, while also minimizing the amount of on-board memory required for the NIC.